1. Field of the Invention
The invention relates to efficient protocol handling by employing multiple, parallel protocol engines in shared memory multiprocessor servers using directory based cache coherence.
2. Discussion of the Prior Art
Processors use on chip or off chip cache memories to speed up accesses to system memory. In a shared memory multiprocessor system, more than one processor may store a copy of the same memory locations (or lines) in the respective cache memories. There has to be a cache coherence mechanism to maintain consistency among the multiple cached copies of the same memory line. In small, bus based multiprocessor systems, the coherence mechanism is usually implemented as a part of the cache controllers using a snoopy coherence protocol.
The snoopy protocol can not be used in large systems that are connected through an interconnection network due to the lack of a bus. As a result, these systems use a directory based protocol to maintain cache coherence. The directories are associated with the main memory and they keep the state information on the memory lines, such as which cache has a copy of the line or whether the line has been modified in a cache, and so on. These directories are used by the coherence controllers to implement the coherence protocol in the system.
The current trend in building large shared memory multiprocessors is to use two 8 way SMPs as nodes, or building blocks. Each node connects to an interconnection network through a coherence controller. The coherence controller includes one or more protocol engines to handle the cache coherence traffic among the nodes. When the number of processors per node increases, and/or the processors become faster, the amount of traffic handled by the protocol engines increases and the protocol engine(s) becomes a performance bottleneck.
Prior art implementations for addressing this problem include the use of two protocol engines: one for local memory requests and one for remote memory requests. However, the local and remote protocol engines may also become system bottlenecks.
It would thus be highly desirable to provide a system that further partitions the memory into finer regions to obtain more parallelism in protocol processing.
An object of the present invention is to provide a system and method for achieving more efficient processing throughput and parallelism in shared multiprocessor memory systems by implementing efficient protocol handling by employing multiple, parallel protocol engines in shared memory multiprocessor servers using directory based cache coherence.
According to the preferred embodiment of the invention, there is provided a system for partitioning the shared memory space into several non-overlapping regions by using address interleaving or using address range registers. Then, one protocol engine may be used to handle references to these memory partitions independently. The multiple protocol engines operate independent of each other and handle the accesses to the corresponding memory regions in parallel. The traffic handled by individual protocol engines is reduced, which results in lower queuing delay and improvement in overall memory access time.